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<a href="#define-members">Macros</a>  </div>
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<div class="title">Interrupt Masks<div class="ingroups"><a class="el" href="group__group__hppass.html">HPPASS       (High Performance Programmable Analog Sub-System)</a> &raquo; <a class="el" href="group__group__hppass__common.html">Common</a> &raquo; <a class="el" href="group__group__hppass__macros.html">Macros</a></div></div>  </div>
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<a name="details" id="details"></a><h2 class="groupheader">General Description</h2>
<p>To be used with <a class="el" href="group__group__hppass__rt__functions.html#ga25b8223ee241be2d737d2d8d1e636122">Cy_HPPASS_GetInterruptStatus</a>, <a class="el" href="group__group__hppass__rt__functions.html#ga224aab393eb9b8fa9cbf40249b7a4d9c">Cy_HPPASS_GetInterruptStatusMasked</a>, <a class="el" href="group__group__hppass__rt__functions.html#ga8e640f7c9f0c7e3622b27e256e1197c5">Cy_HPPASS_ClearInterrupt</a>, <a class="el" href="group__group__hppass__rt__functions.html#ga98877ae8b15b10c0f455b20f953d7c88">Cy_HPPASS_SetInterrupt</a>, <a class="el" href="group__group__hppass__rt__functions.html#ga50d87d33bc8a8336ceabd70566fd42cd">Cy_HPPASS_SetInterruptMask</a>, <a class="el" href="group__group__hppass__rt__functions.html#ga5c63422b1d7cdd30e071e545251a6ee9">Cy_HPPASS_GetInterruptMask</a>. </p>
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Macros</h2></td></tr>
<tr class="memitem:ga477b692d30516f92fe2af421b49074ea"><td class="memItemLeft" align="right" valign="top"><a id="ga477b692d30516f92fe2af421b49074ea"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hppass__interrupts.html#ga477b692d30516f92fe2af421b49074ea">CY_HPPASS_INTR_FIFO_0_OVERFLOW</a>&#160;&#160;&#160;(0x01UL)</td></tr>
<tr class="memdesc:ga477b692d30516f92fe2af421b49074ea"><td class="mdescLeft">&#160;</td><td class="mdescRight">Result interrupt mask for the FIFO #0 overflow. <br /></td></tr>
<tr class="separator:ga477b692d30516f92fe2af421b49074ea"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga611bb82cbd70ee53a68dc4910dd5112d"><td class="memItemLeft" align="right" valign="top"><a id="ga611bb82cbd70ee53a68dc4910dd5112d"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hppass__interrupts.html#ga611bb82cbd70ee53a68dc4910dd5112d">CY_HPPASS_INTR_FIFO_1_OVERFLOW</a>&#160;&#160;&#160;(0x02UL)</td></tr>
<tr class="memdesc:ga611bb82cbd70ee53a68dc4910dd5112d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Result interrupt mask for the FIFO #1 overflow. <br /></td></tr>
<tr class="separator:ga611bb82cbd70ee53a68dc4910dd5112d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac005c14d27d37050cc2584931271f660"><td class="memItemLeft" align="right" valign="top"><a id="gac005c14d27d37050cc2584931271f660"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hppass__interrupts.html#gac005c14d27d37050cc2584931271f660">CY_HPPASS_INTR_FIFO_2_OVERFLOW</a>&#160;&#160;&#160;(0x04UL)</td></tr>
<tr class="memdesc:gac005c14d27d37050cc2584931271f660"><td class="mdescLeft">&#160;</td><td class="mdescRight">Result interrupt mask for the FIFO #2 overflow. <br /></td></tr>
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<tr class="memitem:ga71a7989c5cd102a65df07f90e74a7b36"><td class="memItemLeft" align="right" valign="top"><a id="ga71a7989c5cd102a65df07f90e74a7b36"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hppass__interrupts.html#ga71a7989c5cd102a65df07f90e74a7b36">CY_HPPASS_INTR_FIFO_3_OVERFLOW</a>&#160;&#160;&#160;(0x08UL)</td></tr>
<tr class="memdesc:ga71a7989c5cd102a65df07f90e74a7b36"><td class="mdescLeft">&#160;</td><td class="mdescRight">Result interrupt mask for the FIFO #3 overflow. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hppass__interrupts.html#ga3df0d0a47242c88477711dc9ec9cd8f4">CY_HPPASS_INTR_FIFO_0_UNDERFLOW</a>&#160;&#160;&#160;(0x10UL)</td></tr>
<tr class="memdesc:ga3df0d0a47242c88477711dc9ec9cd8f4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Result interrupt mask for the FIFO #0 underflow. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hppass__interrupts.html#ga0b109017d658673a1a3e1b4a581f48d8">CY_HPPASS_INTR_FIFO_1_UNDERFLOW</a>&#160;&#160;&#160;(0x20UL)</td></tr>
<tr class="memdesc:ga0b109017d658673a1a3e1b4a581f48d8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Result interrupt mask for the FIFO #1 underflow. <br /></td></tr>
<tr class="separator:ga0b109017d658673a1a3e1b4a581f48d8"><td class="memSeparator" colspan="2">&#160;</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hppass__interrupts.html#gab1a4de26664b3b66a7e1ea3580bc5da5">CY_HPPASS_INTR_FIFO_2_UNDERFLOW</a>&#160;&#160;&#160;(0x40UL)</td></tr>
<tr class="memdesc:gab1a4de26664b3b66a7e1ea3580bc5da5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Result interrupt mask for the FIFO #2 underflow. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hppass__interrupts.html#ga88d1a010aba5042d6ba17b47a7ed564d">CY_HPPASS_INTR_FIFO_3_UNDERFLOW</a>&#160;&#160;&#160;(0x80UL)</td></tr>
<tr class="memdesc:ga88d1a010aba5042d6ba17b47a7ed564d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Result interrupt mask for the FIFO #3 underflow. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hppass__interrupts.html#ga242a7acf5d93d53a110f23e5b76acbb9">CY_HPPASS_INTR_FIFO_OVERFLOW</a>&#160;&#160;&#160;(HPPASS_MMIO_HPPASS_INTR_FIFO_OVERFLOW_Msk)</td></tr>
<tr class="memdesc:ga242a7acf5d93d53a110f23e5b76acbb9"><td class="mdescLeft">&#160;</td><td class="mdescRight">FIFO overflow interrupt mask. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hppass__interrupts.html#ga45a935d14dcb6a04704cb4bbdd952565">CY_HPPASS_INTR_FIFO_UNDERFLOW</a>&#160;&#160;&#160;(HPPASS_MMIO_HPPASS_INTR_FIFO_UNDERFLOW_Msk)</td></tr>
<tr class="memdesc:ga45a935d14dcb6a04704cb4bbdd952565"><td class="mdescLeft">&#160;</td><td class="mdescRight">FIFO underflow interrupt mask. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hppass__interrupts.html#ga41d34cb1ff22756476281bda0a82c8ad">CY_HPPASS_INTR_RESULT_OVERFLOW</a>&#160;&#160;&#160;(HPPASS_MMIO_HPPASS_INTR_RESULT_OVERFLOW_Msk)</td></tr>
<tr class="memdesc:ga41d34cb1ff22756476281bda0a82c8ad"><td class="mdescLeft">&#160;</td><td class="mdescRight">Result overflow interrupt mask. <br /></td></tr>
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<tr class="memitem:ga9fdbe3047a6acd1183f8091a449feb2d"><td class="memItemLeft" align="right" valign="top"><a id="ga9fdbe3047a6acd1183f8091a449feb2d"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hppass__interrupts.html#ga9fdbe3047a6acd1183f8091a449feb2d">CY_HPPASS_INTR_GROUP_TR_COLLISION</a>&#160;&#160;&#160;(HPPASS_MMIO_HPPASS_INTR_ENTRY_TR_COLLISION_Msk)</td></tr>
<tr class="memdesc:ga9fdbe3047a6acd1183f8091a449feb2d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sequencer Group Trigger Collision interrupt mask. <br /></td></tr>
<tr class="separator:ga9fdbe3047a6acd1183f8091a449feb2d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga746062ca7c5f2aa982db8cf35f3e41ab"><td class="memItemLeft" align="right" valign="top"><a id="ga746062ca7c5f2aa982db8cf35f3e41ab"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hppass__interrupts.html#ga746062ca7c5f2aa982db8cf35f3e41ab">CY_HPPASS_INTR_GROUP_HOLD_VIOLATION</a>&#160;&#160;&#160;(HPPASS_MMIO_HPPASS_INTR_ENTRY_HOLD_VIOLATION_Msk)</td></tr>
<tr class="memdesc:ga746062ca7c5f2aa982db8cf35f3e41ab"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sequencer Group Hold Violation interrupt mask. <br /></td></tr>
<tr class="separator:ga746062ca7c5f2aa982db8cf35f3e41ab"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga09776ba2aa2cad7b71ab014b8d33f5eb"><td class="memItemLeft" align="right" valign="top"><a id="ga09776ba2aa2cad7b71ab014b8d33f5eb"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hppass__interrupts.html#ga09776ba2aa2cad7b71ab014b8d33f5eb">CY_HPPASS_INTR_AC_INT</a>&#160;&#160;&#160;(HPPASS_MMIO_HPPASS_INTR_AC_INT_Msk)</td></tr>
<tr class="memdesc:ga09776ba2aa2cad7b71ab014b8d33f5eb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Autonomous Controller interrupt mask. <br /></td></tr>
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<tr class="memitem:ga63306fd8f65b4849abb4be4d4202af4d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hppass__interrupts.html#ga63306fd8f65b4849abb4be4d4202af4d">CY_HPPASS_INTR</a></td></tr>
<tr class="memdesc:ga63306fd8f65b4849abb4be4d4202af4d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Combined interrupt mask.  <a href="#ga63306fd8f65b4849abb4be4d4202af4d">More...</a><br /></td></tr>
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<h2 class="groupheader">Macro Definition Documentation</h2>
<a id="ga63306fd8f65b4849abb4be4d4202af4d"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga63306fd8f65b4849abb4be4d4202af4d">&#9670;&nbsp;</a></span>CY_HPPASS_INTR</h2>

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          <td class="memname">#define CY_HPPASS_INTR</td>
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<b>Value:</b><div class="fragment"><div class="line">(HPPASS_MMIO_HPPASS_INTR_FIFO_OVERFLOW_Msk | \</div><div class="line">                                        HPPASS_MMIO_HPPASS_INTR_FIFO_UNDERFLOW_Msk | \</div><div class="line">                                        HPPASS_MMIO_HPPASS_INTR_RESULT_OVERFLOW_Msk | \</div><div class="line">                                        HPPASS_MMIO_HPPASS_INTR_ENTRY_TR_COLLISION_Msk | \</div><div class="line">                                        HPPASS_MMIO_HPPASS_INTR_ENTRY_HOLD_VIOLATION_Msk | \</div><div class="line">                                        HPPASS_MMIO_HPPASS_INTR_AC_INT_Msk)</div></div><!-- fragment -->
<p>Combined interrupt mask. </p>

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